What is the normal resting state of the SET and CLEAR inputs in a NAND gate latch?

What is the normal resting state of the SET and CLEAR inputs in a NAND gate latch?

A. SET = CLEAR = 1
B. SET = 0, CLEAR = 1
C. SET = 1, CLEAR = 0
D. SET = CLEAR = 0

Show Answer

Answer: A

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